Near threshold operation of 16-bit adders in 65nm CMOS technology

The main objective of the thesis is to implement different architectures of 16-bit adders such as; Ripple Carry Adder (RCA), Manchester Carry Chain Adder (MCCA) and Kogge Stone Adder (KSA), in 65nm CMOS technology and to study their performance in terms of power, operating frequency and speed at near threshold operating regions. The performance of these adders are evaluated and compared with each other and a final conclusion is made as to which adder structure is more suitable for implementation in a 65nm technology for low power applications. Several optimisation techniques are performed for the adders to reduce the delay and power consumption. Propagation delay is the most critical or essential parameter to be considered, hence, to minimise the delay of the adder, a technique called sizing and ordering are required for the transistors. The purpose of the thesis is to make a fair comparison among adders over several metrics which include linearity, delay and power. Simulation results of MCCA achieved a greater significant performance upon or over RCA and KSA, and proved it is the best suitable adder for low power applications.